Replace the CUDA-specific batch build switch with
PARSEC_HAVE_DEV_CAPABILITY_BATCH so batching is a runtime capability
shared by all supported device types. Export the new option through
parsec_options and PaRSECConfig.

Add per-device MCA parameters to disable batching for CPU, recursive,
CUDA, HIP, and Level Zero devices. Use shared helpers to sanitize batch
chore types in DTD and to gate GPU task-ring batching on the selected
device.

Teach PTG to accept batch=true for CPU/default bodies as well as typed
device bodies, and add CPU batch examples for both PTG and DTD with
ctest coverage for the enabled and CPU-disabled DTD paths.

Signed-off-by: George Bosilca <gbosilca@nvidia.com>

Add parsec_gpu_task_collect_batch() so GPU submit hooks can build a
batched task ring by providing a compatibility callback, without directly
manipulating the stream pending FIFO.

Always pass a singleton task to the submit hook, and automatically chain a
returned non-singleton task ring into the next GPU stream pending queue.
This removes the need for user-provided completion callbacks whose only
purpose was to merge the batched ring back into fifo_pending.

Update the CUDA GEMM and stage_custom tests to use the new collector helper
and drop their open-coded FIFO iteration and batched completion callbacks.
Use PaRSEC's singleton terminology for the internal task-ring check.

Signed-off-by: George Bosilca <gbosilca@nvidia.com>

Add Doxygen documentation for device task batching, including how to
enable batching for PTG and DTD device chores.

Describe the recommended parsec_gpu_task_collect_batch() interface, its
callback contract, return values, and the runtime behavior for returned
non-singleton task rings.

Also document the lower-level direct FIFO/ring manipulation approach for
expert users that need to avoid the callback overhead in high-load
scenarios.

Link the new page from the main Doxygen page and include it in the
Doxygen input list.

Signed-off-by: George Bosilca <gbosilca@nvidia.com>